A known booster power generating circuit is exemplified in FIG. 2. A circuit arrangement of this booster power generating circuit will be described with reference to FIG. 2.
The booster power generating circuit comprises a signal generating circuit 1 for generating complementary first and second pulse signals S1 and S2 and a charge pump circuit 10 for transferring a given booster potential to the load from an output node N3 in response to the first and second pulse signals S1 and S2.
The charge pump circuit 10 comprises first and second inverters 11-1 and 11-2, first and second capacitors 12-1 and 12-2, first to fourth N-channel MOSFETs (hereinafter referred to as NMOS) 13-1, 13-2, 13-3 and 13-4 and first and second P-channel MOSFETs (hereinafter referred to PMOS) 14-1 and 14-2.
The first and second inverters 11-1 and 11-2 drive respectively the first and second pulse signals S1 and S2 which are output from the signal generating circuit 1, thereby outputting third and fourth pulse signals S3 and S4. The first capacitor 12-1 is connected to the output side of the first inverter 11-1 for boosting the potential of first node N1 in response to the third pulse signal S3. The second capacitor 12-2 is connected to the output side of the second inverter 11-2 for boosting the potential of second node N2 in response to the fourth pulse signal S4. The first node N1 is connected to each source of the first and second NMOSs 13-1 and 13-2 which precharge the first node N1 and also connected to the drain of the first PMOS 14-1 which transfers the potential of the first node N1 to the output node N3. The first NMOS 13-1 is connected to a power potential Vcc at its drain and also connected to the second node N2 at its gate. The second NMOS 13-2 is connected to the power potential Vcc at its drain and gate. The second node N2 is connected to each source of the third and fourth NMOSs 13-3 and 13-4 which precharge the second node N2 and also connected to the drain of the second PMOS 14-2 for transferring the potential of the second node N2 to the output node N3. The third NMOS 13-3 is connected to the power potential Vcc at its drain and also connected to the first node N1 at its gate. The fourth NMOS 13-4 is connected to the power potential Vcc at its drain and gate.
The charge pump circuit 10 is set under the following circuit condition.
Supposing a threshold potential of each of the first to fourth NMOSs 13-1 to 13-4 are represented as vtn and a threshold potential of each of the first and second PMOSs 14-1 and 14-2 are represented as vtp. Potential .phi.p of the load, to be connected to the output node N3, depending on charge consumption I is represented as .phi.p=2 Vcc-vtp in case of I=0 while it is represented as .phi.p=2 Vcc-vtp-.alpha. in case of I=0. Supposing that capacitance of each of the first and second capacitors 12-1 and 12-2 is represented as Cp, parasitic capacitance of each of the first and second nodes N1 and N2 is represented as Cs, potential change of each of the third and fourth pulse signals S3 and S4 is represented as .delta.V and potential change of each of the first and second nodes N1 and N2 is represented as .delta.N, the following equation is established. ##EQU1## where, Cp&gt;&gt;Cs and .delta.N=.delta.V